Overview
In this workshop, you will perform high-level design steps necessary to synthesize, analyze, and verify a multi-voltage design with shutdown requirements using the IEEE 1801 UPF-based Synopsys Eclypse Low-Power Flow. You will:
Identify the library requirements to implement a MV low-power design
Create, modify, interpret, and apply power-intent (UPF) files
Correctly specify PVT requirements for MV low-power optimizations
Perform low-power RTL synthesis using top-down and hierarchical UPF methodologies
Generate a gate level design that is MV-clean
Insert power-domain aware scan chains
Check for logic equivalence of RTL and gate-level designs
Conduct static timing analysis on the pre-layout design
Analyze average and peak power consumptions
Verify the results of running MV rule checks on the gate-level design
?
Objectives
At the end of this workshop, using the Front-End Synopsys Eclypse Low-Power Flow, you should be able to perform the following high-level design objectives:
Create, interpret, and apply UPF files that capture the stated power intent requirements
Synthesize designs for the power intent and power-optimization requirements using both top-down and hierarchical UPF methodologies
Describe the effect of performing a supply-net-aware always-on synthesis
Insert scan chains taking into account the existing power domains while minimizing switching activity
Ensure that the gate-level design is MV clean
Ensure equivalence checking of logic functionality between RTL and gate- level using the design and UPF files
Perform static timing analysis
Generate peak and average power analysis reports/waveforms
Analyze gate-level design for MV rule violations
Write out all needed files for physical implementation
Audience Profile
Logic design and/or verification engineers who have a need to implement, analyze, and verify designs requiring the lowest possible power consumption using the Synopsys Front-End Eclypse Low Power Flow. CAD Engineers and Managers responsible for Low Power flow will also find this workshop beneficial.
?
Prerequisites
To benefit the most from the material presented in this workshop, students need:
?
A basic working knowledge of Synopsys Design Compiler and PrimeTime tools. Working knowledge of the other Synopsys tools used (list at the end of course description) in the workshop is desirable, but not required, to complete this workshop
An awareness of the basics of low-power design techniques. This workshop teaches how to implement these techniques
Course Outline
?
?
1.
Introduction to Low Power Solution
Specifying Power Intent: UPF (Lab)
RTL Synthesis (Lab)
Hierarchical UPF Flow and DFT (Lab)
2.
Lab-4: Hierarchical UPF Flow and DFT (Lab Contd.)
Logic Equivalence Checking (Lab)
Static Timing and Power Analysis (Lab)
Multi Voltage Rule Checking (Lab)?
|
主站蜘蛛池模板：
亚洲精品中文字幕一区
|
激情国产一区二区三区四区小说
|
精品人妻码一区二区三区
|
把插八插露脸对白内射
|
国产精品久久精品牛牛影视
|
91看电影
|
一级毛片免费不卡在线
|
日韩一及片
|
亚洲欧美综合在线观看
|
91精品门国模私拍在线观看
|
99精品国产福利在线观看
|
国产美女做爰免费视频网址
|
色怕怕|
一区二区三区国产精品
|
国产午夜亚洲精品一区网站
|
国产亚洲精品久久久久久久久激情
|
国产精久久一区二区三区
|
91国内外精品自在线播放
|
99久久精品国产片久人
|
玩弄中年熟妇正在播放
|
国产露脸对白porny
|
4438成人成人高清视频
|
一本一本久久a久久综合精品
|
狠狠色丁香婷婷第六色孕妇
|
亚洲一区二区三区无码久久
|
伊人成人在线
|
亚洲精品欧美一区二区三区
|
草久免费视频
|
国产极品精频在线观看
|
欧洲色
|
久久国产精品久久久久久久久久
|
综合激情网
|
日韩一线无码av毛片免费
|
日本人妻丰满熟妇久久久久久
|
大地资源在线观看官网第三页
|
国产真实夫妇视频
|
亚洲精品精华液一区
|
韩国黄色一级视频
|
日韩城人网站
|
少妇高潮惨叫久久久久久电影
|
男人的好看免费观看在线视频
|
總部李老師